DocumentCode
2822632
Title
Systolic multiple-output multipliers for digital signal processing and computer vision
Author
da Fontoura Costa, Luciano ; Sandler, Mark B.
Author_Institution
Dept. of Electron. & Electr. Eng., London Univ., UK
fYear
1991
fDate
11-14 Jun 1991
Firstpage
2633
Abstract
Word-level, bit-serial and bit-level designs for multiplier-less systolic multiple-output multipliers are described. They are characterized in terms of execution speed, hardware requirement and propagation of signals. Their applications to digital signal processing and computer vision are discussed and exemplified respectively by digital filters and a Hough transform
Keywords
VLSI; computerised picture processing; computerised signal processing; digital arithmetic; digital filters; digital signal processing chips; multiplying circuits; systolic arrays; Hough transform; VLSI chip; bit-level designs; bit-serial designs, word-level designs; computer vision; digital filters; digital signal processing; execution speed; hardware requirement; multiple-output multipliers; multiplierless systolic multipliers; signal propagation; Added delay; Adders; Application software; Computer architecture; Computer vision; Digital filters; Digital signal processing; Hardware; Message-oriented middleware; Signal processing algorithms;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 1991., IEEE International Sympoisum on
Print_ISBN
0-7803-0050-5
Type
conf
DOI
10.1109/ISCAS.1991.176086
Filename
176086
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