PROCEDE: a knowledge based system for designing concurrent error detecting VLSI circuits

The authors propose a systematic methodology for designing `reduced cost´ CED VLSI circuits. The framework for the methodology is provided by the prototype electronic computer aided design tool PROCEDE (PROlog based Concurrent Error Detecting Expert). PROCEDE utilises Artificial Intelligence techniques to integrate knowledge concerning various design tasks and CED techniques applicable to various circuit substructures for designing reduced cost on-line testable VLSI circuits