A high speed 256-bit carry look ahead adder design using 22nm strained silicon technology

In this paper, a high speed 256-bit carry look ahead adder has been designed using 22nm strained silicon technology. The proposed adder combines the advantage of both the static and dynamic designs, which exhibits lower leakage, higher noise immunity and high speed. The speed performance of the proposed 256-bit adder is significantly improved by computing the even and the odd carries separately by using two separate Manchester carry chains. The circuit is simulated in HSPICE in the high performance 22nm PTM strained silicon CMOS technology with a supply voltage of V_DD = 0.8V. The simulation results show that the proposed 256bit adder implemented using 8-bit adder modules shows significant operating speed improvement compared to the conventional 256-bit adder based on the standard 4-bit MCC adder modules.