Title :
Review of recent full adders implemented in single electron technology
Author :
Sulieman, Mawahib ; Beiu, Valeriu
Author_Institution :
Sch. of Electr. Eng. & Comput. Sci., Washington State Univ., Pullman, WA, USA
Abstract :
This paper reviews several full adder designs in single electron technology (SET). Different SET designs of full adders were introduced recently. In addition to the structure and size reported for these full adders, this paper also provides a quantitative comparison in terms of delay and power dissipation. This allows for a better understanding of the advantages and disadvantages of each solution. In addition, an improved FA design based on capacitive threshold logic gates are presented.
Keywords :
adders; logic design; logic gates; single electron devices; FA design; SET design; capacitive threshold logic gate; full adder design; power dissipation; single electron technology; Adders; Birth disorders; Capacitance; Capacitors; Circuit simulation; Delay estimation; Electrons; Inverters; Paper technology; Power dissipation;
Conference_Titel :
Circuits and Systems, 2003 IEEE 46th Midwest Symposium on
Print_ISBN :
0-7803-8294-3
DOI :
10.1109/MWSCAS.2003.1562425
