Title :
Delay modeling and design considerations of bipolar multi-input CML gates
Author :
Wu, Tain-Shun ; Wu, Chung-Yu
Author_Institution :
Electron. Res. & Service Organ., Hsinchu, Taiwan
Abstract :
Physical timing models of bipolar CML logic circuits have been developed and successfully applied to the delay analysis and calculation. Moreover, useful design guidelines, requirements, and limitations of CML gates have also been developed. It is expected that the models could be applied in CAD of bipolar VLSI. They could also be extended to model the delay of other bipolar CML-like logic circuits
Keywords :
bipolar integrated circuits; delays; equivalent circuits; integrated logic circuits; logic design; logic gates; CAD; bipolar CML logic circuits; bipolar VLSI; delay analysis; design guidelines; multi-input CML gates; timing models; Capacitance; Delay; Equivalent circuits; Guidelines; Integrated circuit modeling; Inverters; Logic circuits; Logic design; Timing; Voltage;
Conference_Titel :
Circuits and Systems, 1991., IEEE International Sympoisum on
Print_ISBN :
0-7803-0050-5
DOI :
10.1109/ISCAS.1991.176099
