Title :
Parallelism of circuit simulation on array processor
Author :
Jou, Shyh-Jye ; Jen, Chein-Wei ; Shen, Wen-Zen
Author_Institution :
Dept. of Electr. Eng., Central Univ., Taiwan
Abstract :
The intrinsic parallelism of circuit simulation techniques, especially the relaxation-based electrical simulation technique, is analyzed by the dependence graph (DG) representation. The results show that many proposed parallel schemes are the different mappings of these DGs. The hardware array processor architectures for an event-driven MOS timing simulator, EMOTA, are proposed and discussed
Keywords :
circuit analysis computing; digital simulation; field effect transistor circuits; parallel architectures; EMOTA; NCUBE machine; architectures; array processor; circuit simulation; dependence graph; event-driven MOS timing simulator; mappings; relaxation-based electrical simulation; Analytical models; Circuit simulation; Computational modeling; Data mining; Digital circuits; Discrete event simulation; Equations; Hardware; Parallel processing; Timing;
Conference_Titel :
Circuits and Systems, 1991., IEEE International Sympoisum on
Print_ISBN :
0-7803-0050-5
DOI :
10.1109/ISCAS.1991.176109
