Multiplexer based high throughput S-box for AES application

In this paper a multiplexer based S-box architecture with 5 stage pipelining is proposed The proposed AES S-box were implemented on Xilinx device XC5VLX20T Virtex-5 FPGA. The results are compared with modular design architecture. This implementation gives 10.55 ns path delay with the slice area of 52 without pipelining and 1.74 ns path delay with the slice area of 36 by introducing 5 stage pipelining. The results show that the pipelined modified structure reduces the critical path so the through put is increased to 4.5Gbps.