Title :
Design of Power-efficient Memory-based FFT Processor with New Memory Addressing Scheme
Author :
Lee, Seungbeom ; Kim, Hyoungsoon ; Park, Sin-Chong
Author_Institution :
Inf. & Commun. Univ.
Abstract :
This paper presents a new memory-addressing scheme for the realization of power-efficient memory-based FFT processors. The scheme is based on the minimization of the coefficient access and reduction of switching activity by modifying the butterfly sequence. It also results in reducing hardware scale and shortening the critical path delay. Therefore, the power consumption in complex multiplier and memory is reduced
Keywords :
fast Fourier transforms; memory architecture; storage allocation; FFT processor; butterfly sequence; coefficient access minimization; fast Fourier transform; memory addressing scheme; multiplier; power consumption; power-efficient memory; switching activity; Communication switching; Computer architecture; Delay; Discrete Fourier transforms; Energy consumption; Fast Fourier transforms; Hardware; Partitioning algorithms; Radar applications; Radar imaging;
Conference_Titel :
Communications, 2006. APCC '06. Asia-Pacific Conference on
Conference_Location :
Busan
Print_ISBN :
1-4244-0574-2
Electronic_ISBN :
1-4244-0574-2
DOI :
10.1109/APCC.2006.255899
