Systematic design of self-clocked circuits for VLSI applications

In this paper a systematic method is introduced to convert state-machine specifications for self-clocked sequential circuits to be converted into a programme for a PAL structure driving only the clock inputs of edge sensitive flip-flops. In derivation of this method use is made of differential mode state tables which specify the next state as a function of the present state and input changes. Transition equations are obtained for state variables which involve level sensitive as well as edge sensitive inputs. Narrow pulses are generated for edge sensitive inputs which can then be combined with the level sensitive inputs to drive the clock inputs of the flip-flops. It is shown that the `Interface Protocol Asynchronous Cell´ (IPAC) PAL device, recently introduced by `Advanced Micro Devices´ is a suitable structure for this purpose. The general model of an Inhibited Toggle flip-flop is an alternative structure