A systolic node processor for real time high throughput SAR signal processing

Outlines the development and application of a commercially available ASIC technology in a high throughput processor architecture. The device design and production were carried out in the UK and illustrate the level of performance that can be achieved on-shore with readily accessible design tools and technology. The device design, down to verified netlist level, was carried out by signal processing engineers who were using LDS design tools to develop the architecture from a `middle-out´ systems viewpoint. The design cycle for the CVP (complex vector processor) was short, less than 18 months, and the ASIC design methodology produced a complex design that was `right first time´ and operated to specification without the functional hacking that is inherent in full custom designs. The board level designs utilising the CVP provide performance levels that are currently `state-of-the-art´ and indicate that compact, distributed signal processor networks, with node throughputs in excess of 1000 million operations per second, are possible in current UK based technology