An agile ΣΔ fractional-N PLL frequency synthesizer for 2.5G GSM applications

Author

El Sheikh, Mohamed A. ; Sharaf, Khaled ; Haddara, Hisaham ; Ragai, Hani F. ; Marzouk, Mohamed I.

Author_Institution

Electr.Eng. Dept., Ain Shams Univ., Cairo, Egypt

Volume

3

fYear

2003

fDate

27-30 Dec. 2003

Firstpage

1142

Abstract

An agile fractional-N PLL frequency synthesizer is implemented in 0.35μm CMOS technology. A generic transceiver architecture is proposed for 2.5G GSM applications. The synthesizer uses a 26MHz reference frequency, and has 70 KHz loop bandwidth. The synthesizer chip provides agile switching with a settling time of 160 μs for 35MHz frequency step, low in-band noise with 0.5⁰-RMS phase error and fine frequency resolution of less than 50Hz using a new ΣΔ modulator with a dual transfer functions. The synthesizer layout is 1.5 × 1.4 mm². The digital part of the synthesizer operates at 1.5V-supply, while a 3-V supply is used for the analog blocks.

Keywords

CMOS integrated circuits; cellular radio; frequency synthesizers; phase locked loops; sigma-delta modulation; transceivers; 0.35 micron; 1.5 V; 160 mus; 26 MHz; 35 MHz; 70 kHz; CMOS technology; GSM application; agile switching; analog blocks; dual transfer function; fine frequency resolution; fractional-N PLL frequency synthesizer; generic transceiver architecture; phase error; reference frequency; sigma-delta modulator; synthesizer chip; synthesizer layout; Automatic frequency control; Band pass filters; Frequency synthesizers; GSM; Low pass filters; Phase locked loops; Phase noise; Transceivers; Transmitters; Voltage-controlled oscillators;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2003 IEEE 46th Midwest Symposium on

ISSN

1548-3746

Print_ISBN

0-7803-8294-3

Type

conf

DOI

10.1109/MWSCAS.2003.1562495

Filename

1562495