DocumentCode
2824036
Title
VLSI array architecture for Reed-Solomon decoding
Author
Arambepola, B. ; Choomchuay, S.
Author_Institution
GEC-Marconi Res. Centre, Essex, UK
fYear
1991
fDate
11-14 Jun 1991
Firstpage
2963
Abstract
A new architecture is presented for solving a key equation in a Reed-Solomon decoder. This consists of an array of identical cells. The number of cells can be set to meet a given throughput specification. The architecture is briefly compared with other published systolic architectures for the same problem and its advantages and disadvantages are illustrated
Keywords
VLSI; decoding; digital signal processing chips; error correction; systolic arrays; telecommunications computing; Reed-Solomon decoding; VLSI array architecture; array of identical cells; systolic architectures; Argon; Decoding; Equations; Error correction; Error correction codes; Frequency domain analysis; Hardware; Polynomials; Reed-Solomon codes; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 1991., IEEE International Sympoisum on
Print_ISBN
0-7803-0050-5
Type
conf
DOI
10.1109/ISCAS.1991.176167
Filename
176167
Link To Document