Title :
Survivor sequence memory management in Viterbi decoders
Author :
Feygin, Gennady ; Gulak, P. Glenn
Author_Institution :
Dept. of Electr. Eng., Toronto Univ., Ont., Canada
Abstract :
This work extends previous trace-back approaches. A new one-pointer trace-back algorithm for survivor sequence memory management that is particularly well-suited to a VLSI implementation is described. Memory size, latency and implementational complexity of the survivor sequence management are analyzed for both uniprocessor and multiprocessor realizations of Viterbi decoders
Keywords :
VLSI; decoding; digital signal processing chips; error correction; VLSI implementation; Viterbi decoders; implementational complexity; latency; memory size; multiprocessor realizations; one-pointer trace-back algorithm; survivor sequence memory management; trace back memory management; trace-back approaches; uniprocessor; Backpropagation; Decoding; Delay; Energy consumption; Engineering management; Information retrieval; Memory management; Registers; Very large scale integration; Viterbi algorithm;
Conference_Titel :
Circuits and Systems, 1991., IEEE International Sympoisum on
Print_ISBN :
0-7803-0050-5
DOI :
10.1109/ISCAS.1991.176168
