DocumentCode
2824102
Title
A low latency time CORDIC algorithm with increased parallelism
Author
Timmermann, D. ; Hahn, H. ; Hosticka, B.
Author_Institution
Fraunhofer Inst. of Microelectron. Circuits & Syst., Duisburg, Germany
fYear
1991
fDate
11-14 Jun 1991
Firstpage
2975
Abstract
Several methods are presented for increasing the speed of the CORDIC algorithm. First, an improved method is developed which guarantees a constant scale factor when using redundant addition schemes. Then an architecture with increased parallelism is described which considerably reduces, in theory and practice, the CORDIC latency time with a reduced amount of hardware
Keywords
computational complexity; parallel algorithms; redundancy; special purpose computers; CORDIC algorithm; CORDIC latency time; constant scale factor; parallelism; reduced amount of hardware; redundant addition schemes; speed-up; Circuits and systems; Computer architecture; Delay; Equations; Hardware; Inspection; Iterative algorithms; Microelectronics; Parallel processing; Vectors;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 1991., IEEE International Sympoisum on
Print_ISBN
0-7803-0050-5
Type
conf
DOI
10.1109/ISCAS.1991.176171
Filename
176171
Link To Document