Title :
Latched differential FET logic
Author :
Wood, Steven W. ; Smith, Kenneth C. ; Gulak, P. Glenn
Author_Institution :
Dept. of Electr. Eng., Toronto Univ., Ont., Canada
Abstract :
A new circuit topology is proposed for creating complex logic circuits in GaAs. Latched differential FET logic (LDFL) is a fully differential logic family that provides complex logic function capability, tolerance to threshold voltage variations, and complementary, latched-function outputs. LDFL is capable of performing up to eleven levels of logic in one gate, while still giving excellent performance. LDFL also provides improved noise margins due to the use of bootstrapped loads and significantly reduces the load-to-logic ratioing constraint. A nine-level LDFL gate has a delay of 1.7 ns and a static power dissipation of 4 mW as demonstrated in simulations of 4-bit digital comparator circuits
Keywords :
III-V semiconductors; Schottky gate field effect transistors; comparators (circuits); field effect integrated circuits; gallium arsenide; integrated logic circuits; 1.7 ns; 4 bit; 4 mW; GaAs; LDFL; MESFET; bootstrapped loads; circuit topology; complementary outputs; complex logic circuits; complex logic function capability; delay; differential logic family; digital comparator circuits; latched differential FET logic; latched-function outputs; load-to-logic ratioing constraint; logic levels per gate; noise margins; power dissipation; semiconductors; tolerance to threshold voltage variations; Circuit noise; Circuit topology; FETs; Gallium arsenide; Logic circuits; Logic functions; Logic gates; Noise reduction; Signal to noise ratio; Threshold voltage;
Conference_Titel :
Circuits and Systems, 1991., IEEE International Sympoisum on
Print_ISBN :
0-7803-0050-5
DOI :
10.1109/ISCAS.1991.176179
