A 40 nm LP CMOS PLL for high-speed mm-wave communication

Author

Parvais, B. ; Scheir, K. ; Vidojkovic, V. ; Vandebriel, R. ; Vandersteen, G. ; Soens, C. ; Wambacq, P.

Author_Institution

IMEC, Leuven, Belgium

fYear

2010

fDate

14-16 Sept. 2010

Firstpage

254

Lastpage

257

Abstract

A phase-locked loop (PLL) that can be used in a zero-IF radio architecture with beamforming for AV-OFDM with 16-QAM modulation is demonstrated for the first time in 40 nm LP CMOS technology. This type II integer-N PLL of order four includes an injection-locked divide-by-4 prescaler and two quadrature series-coupled VCOs, operating in 63-70 GHz and 72-81 GHz frequency bands. It achieves -85 dBc/Hz in-band phase noise at 64 GHz, corresponding to -19.4 dBc integrated phase noise, while consuming 60 mA from a 1.1 V supply.

Keywords

CMOS integrated circuits; OFDM modulation; millimetre wave devices; nanoelectronics; phase locked loops; quadrature amplitude modulation; voltage-controlled oscillators; 16-QAM modulation; AV-OFDM; LP CMOS PLL; LP CMOS technology; current 60 mA; frequency 63 GHz to 81 GHz; high-speed mm-wave communication; in-band phase noise; injection-locked divide-by-4 prescaler; integrated phase noise; phase-locked loop; quadrature series-coupled VCO; size 40 nm; type II integer-N PLL; voltage 11 V; zero-IF radio architecture; CMOS integrated circuits; Charge pumps; OFDM; Phase locked loops; Phase noise; Tuning;

fLanguage

English

Publisher

ieee

Conference_Titel

ESSCIRC, 2010 Proceedings of the

Conference_Location

Seville

ISSN

1930-8833

Print_ISBN

978-1-4244-6662-7

Type

conf

DOI

10.1109/ESSCIRC.2010.5619881

Filename

5619881