A 60GHz 15.7mW static frequency divider in 90nm CMOS

Two millimeter-wave current mode logic (CML) flip-flop-based static frequency dividers, divide-by-4 and by-2, are realized in a 90nm bulk CMOS. In order to achieve a large locking range and a high operating speed, capacitive-bridged shunt peaking techniques are implemented by taking advantage of the parasitic capacitance. The first flip-flop in these two dividers can directly drive the second flip-flop to save power, resulting in a power consumption as low as of 15.7mW from a 1.2V supply. Their input referred self-resonance frequencies are 57.6GHz and 61.4GHz respectively. Taking into account that all this is achieved in bulk CMOS, and even compared to SOI designs, the achieved power consumption is the lowest reported.