DocumentCode
2824462
Title
An 11b 60MS/s 2.1mW two-step time-interleaved SAR-ADC with reused S&H
Author
Sin, Sai-Weng ; Ding, Li ; Zhu, Yan ; Wei, He-Gong ; Chan, Chi-Hang ; Chio, U-Fat ; Seng-Pan, U. ; Martins, R.P. ; Maloberti, Franco
Author_Institution
Analog & Mixed Signal VLSI Lab., Univ. of Macau, Macao, China
fYear
2010
fDate
14-16 Sept. 2010
Firstpage
218
Lastpage
221
Abstract
An 11b 60MS/s 2-channel two-step SAR ADC in 65nm CMOS is presented. The scheme shares the op-amp between channels for the residual generation and takes advantage of time interleaving for reusing the input S&H of the first stage. A reduction of the gain in the residual generator and sub-threshold operation enables the use of a power-effective, singlestage op-amp with 69dB-gain. The ADC achieves peak SNDR of 57.6dB while consuming 2.1mW from 1-V analog and 0.85-V digital supply, resulting in an FoM of 57fJ/step.
Keywords
CMOS analogue integrated circuits; analogue-digital conversion; operational amplifiers; 2-channel two-step time-interleaved SAR-ADC; CMOS; gain 69 dB; noise figure 57.6 dB; op-amp; power 2.1 mW; residual generation; size 65 nm; subthreshold operation; successive approximation register; voltage 0.85 V; voltage 1 V; Accuracy; Arrays; CMOS integrated circuits; Clocks; Generators; Timing; Transistors;
fLanguage
English
Publisher
ieee
Conference_Titel
ESSCIRC, 2010 Proceedings of the
Conference_Location
Seville
ISSN
1930-8833
Print_ISBN
978-1-4244-6662-7
Type
conf
DOI
10.1109/ESSCIRC.2010.5619890
Filename
5619890
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