• DocumentCode
    2824479
  • Title

    Fast VLSI architectures using non-redundant multibit recoding for computing exponentiation modulo a positive integer

  • Author

    Prasanna, B.S. ; Mohan, P. V Ananda

  • Author_Institution
    Indian Telephone Ind. Ltd., Bangalore, India
  • fYear
    1991
  • fDate
    11-14 Jun 1991
  • Firstpage
    3054
  • Abstract
    Architectures for fast evaluation of A2 mod N have been developed. These are based on the application of the Primlani-Meador technique, recently proposed for nonredundant radix-4 multiplication, together with the technique of E. Lu et al. (1988) for A2mod N evaluation. Complete design details with extensions to multibit recoding considering an even number of bits at a time while requiring the evaluation of fewer partial products are presented
  • Keywords
    computer architecture; cryptography; digital arithmetic; A2mod N evaluation; Primlani-Meador technique; VLSI architectures; computing exponentiation modulo; design details; extensions to multibit recoding; fast evaluation; fast exponentiation; modular multiplication; nonredundant multibit recording; nonredundant radix-4 multiplication; Computer architecture; Concurrent computing; Content addressable storage; Hardware; Iterative methods; Registers; Signal generators; Very large scale integration;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Circuits and Systems, 1991., IEEE International Sympoisum on
  • Print_ISBN
    0-7803-0050-5
  • Type

    conf

  • DOI
    10.1109/ISCAS.1991.176192
  • Filename
    176192
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2824479