A floating point pipeline CORDIC processor with extended operation set

Author

Metafas, D.E. ; Goutis, C.E.

Author_Institution

Dept. of Electr. Eng., Patras Univ., Greece

fYear

1991

fDate

11-14 Jun 1991

Firstpage

3066

Abstract

A novel architecture of a digital signal processing (DSP) floating point, pipelined processor is presented which is based on the CORDIC and CCM algorithms. It provides for the first time a single hardware structure with a full set of elementary arithmetic operations which include circular and hyperbolic functions, square root, logarithm as well as multiplication and division. Its powerful functionality makes it an ideal processing element in high speed multiprocessor applications, e.g. real-time DSP and matrix equation solving problems

Keywords

digital arithmetic; digital signal processing chips; pipeline processing; CCM algorithms; CORDIC processor; circular functions; digital signal processing; division; extended operation set; floating point processor; full set of elementary arithmetic operations; high speed multiprocessor applications; hyperbolic functions; logarithm; matrix equation solving; multiplication; pipelined processor; processing element; real-time DSP; square root; Arithmetic; Computer architecture; Convergence; Digital signal processing; Equations; Hardware; Iterative algorithms; Iterative methods; Pipelines; Signal processing algorithms;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1991., IEEE International Sympoisum on

Print_ISBN

0-7803-0050-5

Type

conf

DOI

10.1109/ISCAS.1991.176195

Filename

176195