VLSI architectures of sparse distributed memory

VLSI hardware architectures of Kanerva´s Sparse Distributed Memory are described. These architectures are designed for high-speed parallel processing with modular expandability. Architectures for an analog address comparator and a systolic array have been developed with advanced structures. Parallel shift register architecture and parallel comparator architecture with binary tree adders have been studied from an effective VLSI implementation point of view. The realization and performance estimations for each architecture are also presented