DocumentCode :
2824571
Title :
Configurable sparse distributed memory hardware implementation
Author :
Lindell, Markku ; Sarrinen, J. ; Tomberg, Jouni ; Kanerva, Pentti ; Kaski, Kimmo
Author_Institution :
Microelectron. Lab., Tampere Univ. of Technol., Finland
fYear :
1991
fDate :
11-14 Jun 1991
Firstpage :
3078
Abstract :
A configurable hardware implementation of Kanerva´s Sparse Distributed Memory has been developed using advanced structures. The system consists of the host computer, address unit and memory unit. The address and memory units have been implemented with commercially available components to two functioning boards, and they perform the Hamming distance comparison and memory storage functions. In order to achieve effective hardware realization the units are designed for highly parallel processing. The host computer is used to edit, compile, and down-load the programs to be run in the units. The performance estimations are also presented
Keywords :
integrated memory circuits; parallel architectures; parallel processing; Hamming distance comparison; Kanerva´s Sparse Distributed Memory; address unit; commercially available components; configurable hardware; hardware realization; host computer; memory storage functions; memory unit; parallel processing; performance estimations; sparse distributed memory hardware implementation; Brain modeling; Counting circuits; Hamming distance; Hardware; Mathematical model; NASA; Prototypes; Random access memory; Read-write memory; Space technology;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Circuits and Systems, 1991., IEEE International Sympoisum on
Print_ISBN :
0-7803-0050-5
Type :
conf
DOI :
10.1109/ISCAS.1991.176198
Filename :
176198
Link To Document :
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