• DocumentCode
    2824585
  • Title

    Power-efficient CIC decimator architecture for fs/4-downconverting digital receivers

  • Author

    Uusikartano, Riku ; Takala, Jarmo

  • Author_Institution
    Inst. of Digital & Comput. Syst., Tampere Univ. of Technol., Finland
  • Volume
    3
  • fYear
    2003
  • fDate
    27-30 Dec. 2003
  • Firstpage
    1315
  • Abstract
    This paper presents a power-efficient cascaded integrator-comb (CIC) decimator architecture for fs/4-downconverting digital receivers. The power saving is based on running all the integrators at half the sampling frequency, regardless of the decimation ratio. This reduction of the maximum clock frequency directly lowers the power consumption, even though the proposed architecture has a larger area than the traditional CIC decimator.
  • Keywords
    cascade networks; frequency convertors; power consumption; radio receivers; cascaded integrator-comb decimator architecture; decimation ratio; digital receivers; maximum clock frequency; power consumption; Baseband; Clocks; Computer architecture; Energy consumption; Filters; Frequency; Modems; Paper technology; Sampling methods; Transceivers;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Circuits and Systems, 2003 IEEE 46th Midwest Symposium on
  • ISSN
    1548-3746
  • Print_ISBN
    0-7803-8294-3
  • Type

    conf

  • DOI
    10.1109/MWSCAS.2003.1562537
  • Filename
    1562537
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2824585