Power-efficient CIC decimator architecture for fs/4-downconverting digital receivers

This paper presents a power-efficient cascaded integrator-comb (CIC) decimator architecture for f_s/4-downconverting digital receivers. The power saving is based on running all the integrators at half the sampling frequency, regardless of the decimation ratio. This reduction of the maximum clock frequency directly lowers the power consumption, even though the proposed architecture has a larger area than the traditional CIC decimator.