A high-linearity low-noise reconfiguration-based programmable gain amplifier

This paper presents a high-linearity low-noise small-size programmable gain amplifier (PGA) based on a new low-noise low-distortion transconductor and a proposed reconfiguration technique. The proposed transconductor combines an inverter-based differential pair with an adaptive biasing circuit to reduce noise and distortion. The reconfiguration technique saves the chip size by half and improves the bandwidth of the amplifier by utilizing the same differential pair for the input transconductance and load-stage, interchangeably. Fabricated in 0.18-μm CMOS, the proposed PGA shows a dB-linear control range of 21dB in 16 steps from -11dB to 10dB with a gain error of less than ±0.33dB, an IIP3 of 7.4÷14.5dBm, a P1dB of -7÷1.2dBm, a noise figure of 13dB, and a 3-dB bandwidth of 270MHz at the maximum gain, respectively. The PGA occupies a chip area of 0.04 mm2 and consumes only 1.3mA from the 1.8V supply.