DocumentCode
2824724
Title
A DRAM interface coprocessor for a low-cost vector microprocessor
Author
Hobson, R.F. ; Li, G. ; Smith, D.
Author_Institution
Sch. of Comput. Sci., Simon Fraser Univ., Burnaby, BC, Canada
fYear
1995
fDate
17-19 May 1995
Firstpage
70
Lastpage
73
Abstract
We describe a 32-bit DRAM interface chip which controls 4 interleaved banks of standard commercial DRAMs with no additional glue chips. The chip performs transparent address translation on the column part of the address during the row access time. Eight zero-wait-state data streams are provided for vector data manipulation
Keywords
CMOS digital integrated circuits; DRAM chips; computer interfaces; coprocessors; interleaved storage; microprocessor chips; storage management chips; vector processor systems; 1.2 mum; 32 bit; CMOS technology; DRAM interface chip; DRAM interface coprocessor; low-cost vector microprocessor; row access time; transparent address translation; vector data manipulation; zero-wait-state data streams; CMOS technology; Communication networks; Coprocessors; DRAM chips; Frequency; Microprocessors; Microwave integrated circuits; Prototypes; Random access memory; Supercomputers;
fLanguage
English
Publisher
ieee
Conference_Titel
Communications, Computers, and Signal Processing, 1995. Proceedings., IEEE Pacific Rim Conference on
Conference_Location
Victoria, BC
Print_ISBN
0-7803-2553-2
Type
conf
DOI
10.1109/PACRIM.1995.519412
Filename
519412
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