Improvement of test data compression using combined encoding

Developments in process technology have led to the design of systems with millions of transistors on a single chip and it has resulted in an increase of test data required to test the circuits. Conventional external testing processes involve storing all test vectors and test responses on the automatic test equipment (ATE) memory. The test data volume for the scan-based test is normally very large due to its single pattern length generated using a combinational automatic test pattern generation (ATPG) tool. The test application time depends on the amount of test data stored on ATE, the time required to transfer the test data from ATE to the core and length of the scan chain. But these testers have limited memory, speed and I/O channels. Efficient test data reduction techniques can reduce the testing time, test power and ATE memory requirements. Three multistage compression techniques are introduced to reduce the test data volume in scan-test applications. The three encoding schemes namely equal run-length coding (ERLC), extended frequency directed run-length (EFDR) coding, alternating variable run-length (AVR) is used for computing the data. These encoding scheme together with nine coded (9C) technique enhance the test compression ratio. In the first stage, pre-generated test cubes with unspecified bits are encoded using nine-coded (9C) scheme. Later the three encoding schemes utilize the properties of compressed data to enhance the test compression. This multistage compression is effective especially when the percentage of don´t care in a test set is very high. The experimental result obtained from ISCAS´89 benchmark circuit confirms the average compression ratio of 46%, 52%, 57% with the proposed 9C-ERLC, 9C-EFDR, 9C-AVR codes respectively.