DocumentCode :
2824763
Title :
Hardware implementation of the RC4 stream cipher
Author :
Kitsos, P. ; Kostopoulos, G. ; Sklavos, N. ; Koufopavlou, O.
Author_Institution :
Dept. of Electr. & Comput. Eng., Patras Univ., Greece
Volume :
3
fYear :
2003
fDate :
27-30 Dec. 2003
Firstpage :
1363
Abstract :
In this paper, an efficient hardware implementation of the RC4 stream-cipher is proposed. In contrary to previous designs, which support only fixed length key, the proposed implementation integrates in the same hardware module an 8-bit up to 128-bit key length capability. Independently of the key length, the proposed VLSI implementation achieves a data throughput up to 22 Mbytes/sec in a maximum frequency of 64 MHz. The whole design was captured by using VHDL language and a FPGA device was used for the hardware implementation of the architecture. A detailed analysis, in terms of performance, and covered area is shown.
Keywords :
circuit CAD; field programmable gate arrays; hardware description languages; very high speed integrated circuits; 64 MHz; FPGA device; RC4 stream cipher; VHDL language; VLSI implementation; hardware implementation; Clocks; Cryptographic protocols; Cryptography; Data security; Design engineering; Frequency; Hardware; Laboratories; Throughput; Very large scale integration;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Circuits and Systems, 2003 IEEE 46th Midwest Symposium on
ISSN :
1548-3746
Print_ISBN :
0-7803-8294-3
Type :
conf
DOI :
10.1109/MWSCAS.2003.1562548
Filename :
1562548
Link To Document :
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