Title :
A high performance, hybrid wave-pipelined linear feedback shift register with skew tolerant clocks
Author :
Nyathi, Jabulani ; Delgado-Frias, Josef G. ; Lowe, Jeff
Author_Institution :
Sch. of Electr. Eng. & Comput. Sci., Washington State Univ., USA
Abstract :
Clock skew and clock distribution are increasingly becoming a major design concern in synchronous pipelined systems. We present a novel high-speed hybrid wave-pipelined linear feedback shift register that manages clock skew by permitting the clock to travel with its associated data through the pipeline. The wave-pipelined clock has a skew 8.34 times lower than that of a buffered clock and is 1.2 times faster.
Keywords :
clocks; shift registers; clock distribution; clock skew; delays clock network; hybrid wave-pipelining; linear feedback shift register; synchronous pipelined systems; wave-pipelined clock; Clocks; Delay systems; Flip-flops; Frequency; Linear feedback shift registers; Logic; Pipeline processing; Propagation delay; Shift registers; State feedback; Hybrid wave-pipelining; clock distribution; clock skew; delays clock network; high-performance; linear feedback shift register; power;
Conference_Titel :
Circuits and Systems, 2003 IEEE 46th Midwest Symposium on
Print_ISBN :
0-7803-8294-3
DOI :
10.1109/MWSCAS.2003.1562553
