Abstract :
While attempts have been made to increase the power of simulators, little regard has been paid to the cost of the result of this work. It will be true to say, though, that a company involved in many digital designs will-in many cases-be prepared to pay large sums for greater throughput. There is still a requirement, though, for organisations that cannot justify the cost of a hardware accelerator, for accelerated simulation. With the ever increasing sizes of designs, simulation times become unacceptably long. This has a number of drawbacks, including: the engineer is held up while the simulation is running, and the longer it goes on, the more expensive it is in terms of lack of productivity; if a simulation takes an appreciable amount of time, the engineer can `loose the thread´ of the function he is testing, even if it is his/her own design, circuit functions would have to be at least partially relearned; a long simulation run-time acts as a bottle neck, holding up perhaps more than just the one engineer. A solution to this problem would be for a system to be able to be grown as cost allow, while giving at the outset of a good price/performance ratio. Methods are proposed in this paper that allow standard high power processing machines to be used as the platforms for novel simulation algorithms
