Reducing energy of digital multiplier by adjusting voltage supply to multiplicand variation

This paper proposes a novel architectural technique to reduce power consumption of digital multipliers. Unlike related approaches which focus on multiplier transition activity, we concentrate on reduction of supply voltage. Two implementation schemes capable of dynamically adjusting a double voltage supply to input data variation are presented. Simulations show that the schemes can reduce energy consumption of 16 × 16 bit multiplier by 33.4% and 25.2% on average without any speed degradation and as low as 4.7% area overhead.