Title :
Variable-way set associative cache design for embedded system applications
Author :
Aly, Ramy E. ; Nallamilli, Bharat R. ; Bayoumi, Magdy A.
Author_Institution :
Center for Adv. Comput. Studies, Louisiana Univ., Lafayette, LA, USA
Abstract :
Variable-way set associative cache is proposed as a new technique to maximize the cache performance especially for embedded applications or to reduce the power consumption with the same performance. Static profiling is used to determine the sets´ behavior of the set-associative cache. Variable-way set-associative can be used in high-performance or low-power operation modes. Each set in the proposed design basically has different associativity to maximize the total performance for the cache size or reduce the power consumption. The proposed architecture is simulated on SimpleScalar simulator and tested on several Spec2000 Benchmarks. The results show on average 2% reduction in the miss rate at the high-performance mode and up to 43% reduction of the power consumption at low-power mode.
Keywords :
cache storage; content-addressable storage; embedded systems; low-power electronics; memory architecture; SimpleScalar simulator; Spec2000 Benchmarks; associativity; cache design; cache size; computer architecture; embedded system; low-power operation modes; memory architecture; miss rate reduction; power consumption; static profiling; variable-way set associative cache; Benchmark testing; Computational modeling; Computer architecture; Costs; Degradation; Embedded system; Energy consumption; Hardware; Memory architecture; Power generation economics; cache design; computer architecture; memory architecture; set-associative cache;
Conference_Titel :
Circuits and Systems, 2003 IEEE 46th Midwest Symposium on
Print_ISBN :
0-7803-8294-3
DOI :
10.1109/MWSCAS.2003.1562565
