Technology portable analytical model for DSM CMOS inverter transition time estimation

In this paper, we propose a new analytical model to estimate the transition time of CMOS inverters. Accounting for the main effects of deep sub-micron such as velocity saturation and mobility degradation, the relationship between the input and output transition is discussed and captured by a closed-form expression. The developed model has been formulated to depend only on device model parameters, which are usually provided with the given technology. The proposed model was verified against circuit simulation using Spectre level 11 (BSIM3v3) for a wide range of transistor sizes, output loading and input transition times. It has also been tested for portability between 0.25 μm, 0.18 μm and 0.13 μm technologies Our model showed good accuracy compared to simulation with maximum error of 10% and an average error of 4%.