A high-level optimization scheme for low power clock design

Power consumption due to clock signals has been a major concern in synchronous VLSI chip design. This paper proposes a high-level power optimization scheme with two techniques: operator chaining, multiple clock. Chaining the operators with shorter delay allows the use of a lower clock frequency. With multiple clocks, the operators with longer delay can be driven by another clock with lower frequency. These techniques can be combined with clock gating to further reduce clock power consumption. The experiments with benchmarks show that the clock power reduction rate and total power savings are around 46% and 15%, on average, respectively, with a little or no performance degradation.