A yield enhancing router

Author

Balachandran, K. ; Bhaskaran, S. ; Ganesan, H. ; Lursinsap, C.

Author_Institution

Center of Adv. Comput. Studies, Southwestern Louisiana Univ., Lafayette, LA, USA

fYear

1991

fDate

11-14 Jun 1991

Firstpage

1936

Abstract

The authors present an iterative routing algorithm that maximizes the yield of a routing solution by reducing the critical areas in the channel that are the sources for potential bridging faults, caused by spot defects. The algorithm serves to reduce the number of critical areas in a routing solution without increasing the total area, the number of tracks, or the distance between tracks. This algorithm is independent of whether the preliminary solution was obtained using a grid- or a gridless-based channel router. The approach uses unused silicon area to dogleg nets. The algorithm is general to the extent that it can be programmed to execute in a parallel environment. Results obtained have been tabulated and show an improvement in the yield and reliability of the routing solution

Keywords

circuit layout CAD; iterative methods; parallel algorithms; channel router; iterative routing algorithm; parallel environment; yield enhancing router; Circuit faults; Compaction; Costs; Iterative algorithms; Production; Routing; Silicon; Tellurium; Very large scale integration; Wires;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1991., IEEE International Sympoisum on

Print_ISBN

0-7803-0050-5

Type

conf

DOI

10.1109/ISCAS.1991.176252

Filename

176252