Low power architectures for the MAP decoder with optimized memory sizes

In the context of iterative decoding using the turbo codes, the Log-MAP algorithm offers the best performance when compared to the Max-Log-MAP and the Viterbi algorithms. Decoders employing the Log-MAP algorithm require large amount of memory as either the forward or backward state metrics have to be stored for the whole block being processed, before the final log likelihood decisions are obtained. Hence, memory optimization is a vital issue in the implementation of the Log-MAP decoder. In this paper, the authors introduced a number of low power VLSI architectures for the Log-MAP decoder employing a reduced complexity technique of the forward recursive computation of the reverse state metrics in order to reduce memory storage. Power reduction in these decoder architectures is discussed for various sub-block lengths and compared with the conventional implementation of the Log-MAP decoder. The results demonstrated up to 35% power reduction.