Title :
A simulation-based temporal assertion checker for PSL
Author :
Chang, Kai-Hui ; Tu, Wei-Ting ; Yeh, Yi-Jong ; Kuo, Sy-Yen
Author_Institution :
Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan
Abstract :
A simulation-based temporal assertion verification engine for PSL (property specification language), called Tempral Wizard, is proposed in this paper. It is very efficient because its time and space complexity are both O(n). A new concept, tag, is introduced in Tempral Wizard and it handles the forall operator elegantly.
Keywords :
computational complexity; electronic design automation; formal verification; simulation; temporal logic; PSL; Tempral Wizard; property specification language; space complexity; temporal assertion verification engine; time complexity; Circuit simulation; Circuit synthesis; Clocks; Engines; Formal specifications; Hardware design languages; Logic; Specification languages; Terminology; Yarn;
Conference_Titel :
Circuits and Systems, 2003 IEEE 46th Midwest Symposium on
Print_ISBN :
0-7803-8294-3
DOI :
10.1109/MWSCAS.2003.1562587
