Title :
An analysis of a fault tolerant scheme for processor ensembles
Author :
Upadhyaya, S.J. ; Chakravarty, S.
Author_Institution :
Dept. of Electr. & Comput. Eng., State Univ. of New York, Buffalo, NY, USA
Abstract :
The authors present and analyze a locally redundant (LR) scheme, applicable to a number of interconnection topologies, for designing fault tolerant processor ensembles. A switching structure is presented for reconfiguration, and it is shown that the LR scheme is area-efficient. A model for static analysis (yield) that takes into account processor, switch, and link failures is presented. This dynamic analysis, based on Markov models, includes the determination of operational availability of the fault tolerant system with and without graceful degradation. Closed-form expressions are also obtained for the transition probabilities of the Markov models in terms of the system parameters
Keywords :
Markov processes; fault tolerant computing; multiprocessor interconnection networks; Markov models; area-efficient; closed-form expressions; dynamic analysis; fault tolerant processor ensembles; graceful degradation; interconnection topologies; link failures; locally redundant scheme; operational availability; processor failures; reconfiguration; static analysis; switch failures; switching structure; system parameters; transition probabilities; yield; Binary trees; Circuit faults; Concurrent computing; Design engineering; Distributed computing; Failure analysis; Fault tolerance; Parallel processing; Switches; Topology;
Conference_Titel :
System Sciences, 1990., Proceedings of the Twenty-Third Annual Hawaii International Conference on
Conference_Location :
Kailua-Kona, HI
DOI :
10.1109/HICSS.1990.205105
