DocumentCode
282550
Title
Hazard prevention in combinational circuits
Author
McGeer, Patrick C. ; Brayton, Robert K.
Author_Institution
Dept. of Comput. Sci., British Columbia Univ., Vancouver, BC, Canada
Volume
i
fYear
1990
fDate
2-5 Jan 1990
Firstpage
111
Abstract
The authors consider the problem of hazard prevention in combinational circuits. It is shown that only precharged-unate circuits do not undergo hazards (multiple change in a node´s value) during evaluation. It is further shown that the addition of redundancy and ordering information on the inputs to a gate in a circuit or the insertion of delay elements cannot prevent the occurrence of hazards in an inherently hazardous circuit
Keywords
combinatorial circuits; hazards and race conditions; redundancy; combinational circuits; delay elements; gate inputs; hazard prevention; multiple change; node value; ordering information; precharged-unate circuits; redundancy; Circuit synthesis; Clocks; Combinational circuits; Computer science; Contracts; Delay; Hazards; Steady-state; Switches; Timing;
fLanguage
English
Publisher
ieee
Conference_Titel
System Sciences, 1990., Proceedings of the Twenty-Third Annual Hawaii International Conference on
Conference_Location
Kailua-Kona, HI
Type
conf
DOI
10.1109/HICSS.1990.205106
Filename
205106
Link To Document