Title :
Efficient implementation of bit-level signal processors
Author :
Ait-Boudaoud, D. ; Ibrahim, M.K.
Author_Institution :
Dept. of Electr. & Electron. Eng., Nottingham Univ, UK
Abstract :
Two efficient bit-level systolic processors using a single phase clocking scheme are presented. The novel architecture adopted for these arrays is based on a cell merging approach. This has reduced the number of pipelining latches, and yet it has kept the clock cycle unchanged from that of a conventional gated full-adder cell. Both arrays have their latency independent of their sizes. The result of a simulation of the basic cell showed that the arrays could operate at 100 MHz. This simulation was based on a 2-μm CMOS p-well process
Keywords :
CMOS integrated circuits; VLSI; digital signal processing chips; systolic arrays; 100 MHz; 2 micron; CMOS p-well process; array architecture; bit-level signal processors; cell merging approach; cell simulation; clock cycle; pipelining latches; single phase clocking scheme; systolic processors; Clocks; Convolution; Convolvers; Delay; Equations; Latches; Merging; Pipeline processing; Signal processing; Throughput;
Conference_Titel :
Circuits and Systems, 1991., IEEE International Sympoisum on
Print_ISBN :
0-7803-0050-5
DOI :
10.1109/ISCAS.1991.176268
