Efficient implementation of bit-level signal processors

Two efficient bit-level systolic processors using a single phase clocking scheme are presented. The novel architecture adopted for these arrays is based on a cell merging approach. This has reduced the number of pipelining latches, and yet it has kept the clock cycle unchanged from that of a conventional gated full-adder cell. Both arrays have their latency independent of their sizes. The result of a simulation of the basic cell showed that the arrays could operate at 100 MHz. This simulation was based on a 2-μm CMOS p-well process