Low-power VLSI architectures for 3D discrete cosine transform (DCT)

The 3D discrete cosine transform (DCT) extends the energy compaction properties of conventional 2D-DCT to integral 3D images and to the spatio-temporal coding of 2D video sequences. This paper addresses the problem of a cost-effective VLSI realization of the 3D-DCT and its inverse (IDCT). The VLSI design space is exploited at different levels of abstraction (algorithm, architecture, circuit, technology) to devise a family of 3D-DCT/IDCT macrocells that, implemented in a 0.18 μm CMOS technology, support the real-time processing of main video formats with different trade-offs between circuit complexity and power consumption. A clock-gating design strategy further reduces power consumption according to input signal statistics.