A processor approach for video signal processing

Author

Caesar, Knut ; Richardson, Andrew ; Himmel, Thomas ; Schmidt, Ulrich ; Langmeier, Ingo ; Uhlenhoff, Arnold

Author_Institution

ITT Intermetall, Freiburg, Germany

fYear

1991

fDate

11-14 Jun 1991

Firstpage

57

Abstract

The authors present a signal processor, that is designed as a basic cell for multiprocessor arrays. A high-instruction-rate, 12-b data width, and a RISC (reduced instruction set computer) cell architecture make the processor suitable for the requirements of video signal processing. The multiprocessor array belongs to the class of the multiple-instruction multiple-data (MIMD) principle, which offers high performance and flexibility due to the programmability of each cell. The obtained MIMD topology is an orthogonal net of processors where each processor communicates with its neighbors

Keywords

computerised signal processing; digital signal processing chips; parallel architectures; pipeline processing; reduced instruction set computing; video signals; MIMD topology; RISC cell architecture; cell programmability; high level parallelism; high-instruction-rate; multiple instruction multiple data principle; multiprocessor arrays; orthogonal net of processors; signal processor; video signal processing; Circuit topology; Clocks; Frequency synchronization; HDTV; Parallel processing; Pipeline processing; Process design; Signal design; Signal processing; Video signal processing;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1991., IEEE International Sympoisum on

Print_ISBN

0-7803-0050-5

Type

conf

DOI

10.1109/ISCAS.1991.176272

Filename

176272