Title :
Multiprocessor cache simulation using hardware collected address traces
Author :
Wilson, Andrew W., Jr.
Author_Institution :
Encore Comput. Corp., Marlborough, MA, USA
Abstract :
An evaluation is presented of the performance of large private caches for multiprocessors using hardware-collected address traces. The traces are 14-million memory references in length and are collected from one processor of a multiprocessor in real time. Both uniprocessor performance and multiprocessor time-sliced performance are simulated. The effects of cache size for large caches, process migration, and cache coherency on hit ratio and bus traffic are measured. Conclusions regarding the benefits of large private caches in a time-shared multiprocessor environment are reached
Keywords :
buffer storage; multiprocessing systems; performance evaluation; bus traffic; cache coherency; hardware collected address traces; memory references; multiprocessor cache simulation; process migration; time-sliced performance; uniprocessor performance; Application software; Computational modeling; Contracts; Hardware; Operating systems; Size measurement; Software performance; Traffic control; Voice mail; Wiring;
Conference_Titel :
System Sciences, 1990., Proceedings of the Twenty-Third Annual Hawaii International Conference on
Conference_Location :
Kailua-Kona, HI
DOI :
10.1109/HICSS.1990.205123