A new architecture of median filters with linear hardware complexity

A novel algorithm of median filters for VLSI implementation is proposed. The architecture based on this algorithm has modular, regular, locally connected and expansible features. The throughput of the filter is independent of the window size and the hardware complexity is O (WN), where W is the window size and N is the bit number per pixel. The algorithm is based on storing an ordered list of the input data and updating the list as a new datum arrives. The new input datum is compared, in parallel, with all the values in the ordered list to find the position where it can be inserted into the list. This approach is efficient in hardware and suitable for fast software implementation. An application to 2D image processing is discussed