A new architecture of median filters with linear hardware complexity

Author

Tsai, C.J. ; Lu, E.H. ; Chen, C.H. ; Lee, J.Y. ; Jou, I.-C.

Author_Institution

Dept. of Electr. Eng., Nat. Cheng Kung Univ., Tainan, Taiwan

fYear

1991

fDate

11-14 Jun 1991

Firstpage

101

Abstract

A novel algorithm of median filters for VLSI implementation is proposed. The architecture based on this algorithm has modular, regular, locally connected and expansible features. The throughput of the filter is independent of the window size and the hardware complexity is O (WN), where W is the window size and N is the bit number per pixel. The algorithm is based on storing an ordered list of the input data and updating the list as a new datum arrives. The new input datum is compared, in parallel, with all the values in the ordered list to find the position where it can be inserted into the list. This approach is efficient in hardware and suitable for fast software implementation. An application to 2D image processing is discussed

Keywords

VLSI; digital filters; parallel algorithms; parallel architectures; picture processing; 1D algorithm; 2D image processing; VLSI implementation; linear hardware complexity; median filters; Computer architecture; Counting circuits; Filtering algorithms; Hardware; Image processing; Laboratories; Low pass filters; Nonlinear filters; Registers; Signal processing algorithms;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1991., IEEE International Sympoisum on

Print_ISBN

0-7803-0050-5

Type

conf

DOI

10.1109/ISCAS.1991.176283

Filename

176283