Title :
I/O scheme for video signal processing application to image filtering
Author :
Jutand, F. ; Mou, Z.J. ; Demassieux, N.
Author_Institution :
Telecom Paris Univ., France
Abstract :
The authors examine VLSI architectural I/O constraints for achieving single-chip real-time implementation of image processing. As an illustration of the potential of this approach, the architecture of a 16×16, fixed kernel, 54 MHz convolver has been devised and evaluated
Keywords :
VLSI; computerised picture processing; digital signal processing chips; real-time systems; systolic arrays; 54 MHz; DSP; I/O scheme; VLSI architectural I/O constraints; convolver; image filtering; image processing; real-time implementation; single-chip; snake scanning; video signal processing; Clocks; Computer architecture; Convolution; Filtering; Image processing; Image storage; Kernel; Memory architecture; Pixel; Video signal processing;
Conference_Titel :
Circuits and Systems, 1991., IEEE International Sympoisum on
Print_ISBN :
0-7803-0050-5
DOI :
10.1109/ISCAS.1991.176304
