Modular VLSI architectures for real-time vector quantization

The authors propose modular linearly connected VLSI architectures for VQ (vector quantization) which can support real-time image processing applications. The design considered requires fixed memory bandwidth with the host and allows codebook changes. The throughput is independent of the codebook size. Each processing element consists of an adder and a shift register instead of a multiplier. These designs can be extended to the case when a fixed number of processors are available. A number of VQ schemes such as single-stage and multistage VQ and classified VQ can be implemented using this approach