VHDL design of an ATM switch

Author

Gilderson, J. ; El-Guibaly, E. ; Bhargava, V.K.

Author_Institution

Dept. of Electr. & Comput. Eng., Victoria Univ., BC, Canada

fYear

1995

fDate

17-19 May 1995

Firstpage

100

Lastpage

103

Abstract

An ATM switch must be capable of not only routing a user data cell from an input to an output port, it must also be capable of interpreting and processing ATM signalling and management cells. The VHDL design of an ATM layer switch meeting these requirements is discussed. The switching requirements of the different layers of the protocol model is presented based on standards documents. In addition, ways of dividing the functionality of the management and signalling planes are described with the goal of optimizing the performance of the ATM switching system

Keywords

asynchronous transfer mode; hardware description languages; telecommunication computing; telecommunication network management; telecommunication signalling; telecommunication standards; telecommunication switching; ATM layer switch; ATM management cells; ATM signalling cells; ATM switch; ATM switching system; VHDL design; performance optimisation; protocol model; standards documents; Asynchronous transfer mode; Engineering management; Optical switches; Physical layer; Protocols; Quality of service; Routing; SONET; Signal processing; Switching systems;

fLanguage

English

Publisher

ieee

Conference_Titel

Communications, Computers, and Signal Processing, 1995. Proceedings., IEEE Pacific Rim Conference on

Conference_Location

Victoria, BC

Print_ISBN

0-7803-2553-2

Type

conf

DOI

10.1109/PACRIM.1995.519419

Filename

519419