Sensitivity analysis of generic on-chip ΔI-noise simulation methodology

Power integrity, i.e. providing a stable voltage supply under the condition of rapidly changing current transients, gets increasing attention in the design of electronic packaging. Part of this discussion is the on-chip ΔI-noise. Various simulation methodologies, e.g. RAPiD, are known for simulation. Characteristic for these simulations is the very time consuming task of collecting and processing the complex input data, in order to optimise the required effort a sensitivity analysis for high-frequency on-chip ΔI-noise simulation has been carried out. This paper describes the results of this sensitivity analysis. A generic description of the on-chip ΔI-noise simulation methodology is shown. In particular the required input data is described. The sensitivity analysis quantifies the impact of each simulation parameter on the simulation results. The nominal value of each input parameter has been varied in a range from 0.5x to 2.0x compared to a nominal case. The maximum HF ΔI-noise is measured and plotted versus the respective input parameter deviation. The input parameters are categorized in high, medium and low impact parameters. This analysis results in guidelines which design parameters most efficiently reduce HF-noise and/or which input parameter need to be accurate in order to obtain accurate simulation results.