Influence of damping and voltage dependent leakage resistance on mid-frequency power noise

Author

Garben, Bernd ; Paech, Andreas

Author_Institution

IBM Deutschland Entwicklung GmbH, Germany

fYear

2004

fDate

9-12 May 2004

Firstpage

45

Lastpage

48

Abstract

Accurate predictions of power/ground-noise are essential for adequate chip and package design. This paper studies especially the influence of damping and leakage on the mid-frequency power noise caused by switching activity variations of logic circuits. The noise is determined by simulations and calculated by a closed form expression which is derived for a simplified 2D circuit representation of the chip and package power delivery network. Both approaches agree within 16%. The voltage dependency of the leakage resistance is found to be essential for the power noise when the noise is determined by the resonance between on-die capacitors and the next stage of decoupling capacitors. It is shown that damping and leakage reduce significantly the influence of the on-die decoupling capacitance and package capacitor inductance on the mid-frequency power noise.

Keywords

capacitors; damping; integrated circuit design; integrated circuit noise; integrated circuit packaging; logic circuits; 2D circuit representation; chip design; chip power delivery network; damping influence; decoupling capacitors; logic circuits; mid-frequency power noise; on-die capacitors; on-die decoupling capacitance; package capacitor inductance; package design; package power delivery network; power/ground-noise; voltage dependency; voltage dependent leakage resistance; Capacitance; Capacitors; Circuit noise; Circuit simulation; Damping; Logic circuits; Packaging; Resonance; Switching circuits; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Signal Propagation on Interconnects, 2004. Proceedings. 8th IEEE Workshop on

Print_ISBN

0-7803-8470-9

Type

conf

DOI

10.1109/SPI.2004.1408999

Filename

1408999