Title :
A parallel architecture for high-speed analog Viterbi detectors
Author :
Spencer, Richard R.
Author_Institution :
Dept. of Electr. Eng. & Comput. Sci., California Univ., Davis, CA, USA
Abstract :
A parallel architecture for an analog implementation of the Viterbi algorithm is presented. The implementation uses mostly continuous-time circuitry to achieve high speed and low complexity. The architecture also allows the designer to reduce the sampling rate required for a given baud rate at the expense of additional circuitry
Keywords :
analogue circuits; decoding; detector circuits; parallel architectures; signal detection; analog Viterbi detectors; continuous-time circuitry; high-speed; low complexity; parallel architecture; sampling rate; Bit error rate; Detectors; Gaussian noise; Laboratories; Magnetic recording; Parallel architectures; Polynomials; Probability; Solid state circuits; Viterbi algorithm;
Conference_Titel :
Circuits and Systems, 1990., Proceedings of the 33rd Midwest Symposium on
Conference_Location :
Calgary, Alta.
Print_ISBN :
0-7803-0081-5
DOI :
10.1109/MWSCAS.1990.140900
