Title :
Design of low voltage ultra high-speed 1:16 DEMUX by 0.18μm CMOS process
Author :
Feng, Xie ; Yanyi, Xu
Author_Institution :
Sch. of Electron. Eng., Navy Univ. of Eng., Wuhan, China
Abstract :
This paper describes a low power dissipation super high speed 1:16 demultiplexer using SMIC 0.18μm CMOS (Complementary Metal Oxide Semiconductor) RF process. The tree-type structure is adopted. Single-ended dynamic load latch is proposed for high speed 1:2 demultiplexer cell while CMOS quasi-static flip flop for medium speed 1:2 demultiplexer cell and dynamic CMOS logic for low speed 1:2 demultiplexer. The concrete circuits are composed of latches, frequency dividers and I/O buffers. Output data rate is up to 10-Gb/s. The total power consumption of the chip is about 100mW at a supply voltage of 1.2V.
Keywords :
CMOS logic circuits; demultiplexing equipment; flip-flops; frequency dividers; CMOS quasistatic flip flop; I-O buffers; SMIC CMOS RF process; bit rate 10 Gbit/s; complementary metal oxide semiconductor RF process; demultiplexer cell; dynamic CMOS logic; frequency dividers; low-power dissipation; low-voltage ultrahigh-speed DEMUX; single-ended dynamic load latch; size 0.18 mum; tree-type structure; voltage 1.2 V; CMOS logic circuits; CMOS process; CMOS technology; Circuit synthesis; Clocks; Design engineering; Energy consumption; Latches; Low voltage; Power engineering and energy; CMOS; demultiplexer; low power; optical communication; ultra-high speed;
Conference_Titel :
Future Computer and Communication (ICFCC), 2010 2nd International Conference on
Conference_Location :
Wuhan
Print_ISBN :
978-1-4244-5821-9
DOI :
10.1109/ICFCC.2010.5497514
